Jinkyu Lee et al developed a LFSR reseeding scheme. In, it is shown that different LFSR architecture affects the power consumed and the hardware used. In this paper, redundancy is introduced during testing and this reduces the power consumption without affecting the fault coverage. Corno et al has proposed for the low power test pattern generation for sequential circuit. There are various advantages of test pattern generation at a higher level than the gate level. In approach, a fault model and ATPG algorithm is chosen first and then test pattern are generated to obtain the desired fault coverage. This reduces the average and peak power of circuit during testing. This approach proposed a low transition LFSR for BIST applications. In this method, power consumption is reduced but at the additional cost is between 19% and 13% Another technique was proposed in. One method is to use Random Single Input Change (RSIC) test generation, which is used to generate low power test pattern. Some of the earliest work that has been proposed for optimizing the power during testing is discussed in this section of the paper. There has been various low power approaches proposed to solve the problem of power dissipation during the testing.

But in other testing techniques, circuits are added to lower the frequency of circuit during test. As the circuit is designed in the deep sub micron (DSM) technology, this uses small supply voltages and hence this reduces the use of special cooling equipment to remove the excessive heat during test.The excessive noise can change the logic state of the circuit lines leading good dies to fail the test and hence loss of yield. High power and ground noise caused by high switching during testing are serious problem where the supply connects are poor.Low power dissipation during test application is thus becoming an equally important figure of merit in today‘s VLSI circuits design and is expected to become one of the major objectives in the near future.

The increased power may be responsible for cost, reliability, performance verification, autonomy and technology related problems.This is due to lack of correlation between theSuccessive test patterns generated by ATPG (for external testing) or LFST (for BIST) and this large power dissipation cases following effects: During testing large power is dissipated than in the normal mode.

Linear feedback shift register ppt